More and more people are relying on the Internet to conduct financial transactions, make telephone calls, and perform video conferences. Loss of data could have a devastating effect including loss or delay of critical financial transactions, interference from annoying noises from the telephone lines, or distortion in video clips. To address these problems, redundancy protection may be built into communication systems. One type of redundancy protection that can be utilized at an input terminal for terminating transmission lines of the communication system employs a hardware protection scheme using a primary line interface unit (LIU) card and a secondary or backup LIU card. In the event that there is a primary card failure, data transmission can be switched to the backup card and data transmission can be continued. One type of switching scheme is called hitless protection switching (HPS), where framing synchronization is not lost in the switch between the primary card and the backup card.
The transmission of information over transmission lines also requires an input termination impedance at the receiving side that matches the characteristic impedance of the transmission line. For example, in T1/E1/J1 long haul/short haul communication systems, the impedance matching requires that the termination impedance of the primary card and the backup card be selectable from line terminating impedances 75 Ohm, 100 Ohm, 110 Ohm, or 120 Ohm (T1:100, J1:110, E1:75/120).
In an application such as a HPS, the primary and backup cards are coupled together. In normal operation, the primary card is set to the desired impedance, and the backup card is required to be in a high impedance state whether the power on the backup card is on or off. An exemplary backup card circuit is shown in FIG. 3 (discussed further below). Typically, if the backup card is powered on, high resistance can be achieved by purposefully cutting off the conductive circuit on the backup card. However, when the backup card is powered off (which happens in circumstances such as replacing a LIU card in the system and the like), a low impedance conductive loop may be formed through the backup card (which will be described in detail below), and that low impedance loop may affect the function of the primary card.
Typically, there are two connection modes between the primary card and the backup card. One type of connection is the line connection mode. As shown in FIG. 1, in the line connection mode, a primary card 120 and a backup card 122 are both coupled to the same input line through transformers 124 and 126. The other connection is the pin-pin connection mode. As shown in FIG. 2, in the pin-pin connection mode, backup card 122 and primary card 120 are both coupled to the output terminals of a transformer 128. In either connection mode, a low impedance loop may be formed through the backup card at power off.
FIG. 3 shows a simplified circuit diagram of a traditional input termination circuit 100 that can be used in backup card 122. Input termination circuit 100 can be set to provide high impedance between terminals RTIP (receiver differential tip positive input) and RRING (receiver differential ring negative input) when power is on, and also can be set to provide a low impedance termination during an operational mode, i.e., when circuit 100 becomes a primary card.
As shown in FIG. 3, the input termination circuit 100 includes terminals RTIP and RRING, a common mode voltage (VCM) buffer circuit 102, a termination impedance matching circuit 104, a control circuit 106, and a bias circuit 108. Input termination circuit 100 is coupled to an internal circuit (not shown) (e.g., a device that processes the signals received through input termination circuit 100) through monitor switches 132 and 134.
VCM buffer circuit 102 includes a reference voltage Vref, an amplifier 103, a PMOS (denoted as PM2) and an NMOS (denoted as NM2) coupled in series between a power supply VDD and ground. Vref is coupled to an input of amplifier 103 and transistors PM2 and NM2 having their gates respectively coupled to two outputs of amplifier 103. In some embodiments, Vref can be about 1.5 V. Bias circuit 108 includes two resistors R3 and R4 coupled in series between RTIP and RRING. Resistors R3 and R4 are usually at least about 10K Ohm. When power is on, VCM buffer provides a 1.5 V bias voltage to a node 302 between resistors R3 and R4.
As shown in FIG. 3, control circuit 106 includes two transistors, a PMOS (denoted by PM3) and an NMOS (denoted by NM3) coupled between VDD and ground. Transistors PM3 and NM3 have their gates coupled to a register configuration circuit 107, which may provide a control signal to turn transistors PM3 and NM3 on or off. Termination impedance matching circuit 104 includes a transistor NM1, which can be an NMOS transistor, and two resistors R1 and R2. Resistors R1 and R2 each have a resistance of about half of a line termination resistance, which may be selected from 75 Ohm, 100 Ohm, 110 Ohm, or 120 Ohm depending on the standard. Transistor NM1 is controlled by a control signal CTL generated by control circuit 106 at a node 304 between the two transistors PM3 and NM3 of control circuit 106.
In line connection mode, as shown in FIG. 1, primary card 120 and backup card 122 are respectively coupled to transmission lines through transformers 124 and 126. Backup card 122 may employ input termination circuit 100 as shown in FIG. 3. Transformers 124 and 126 isolate DC signals and couple AC signals to primary card 120 and backup card 122. Typically, primary card 120 is operating and, in backup card 122, control circuit 106 provides a negative control voltage CTL, which turns off transistor NM1. The circuit between RTIP and RRING in circuit 100 has high impedance corresponding to R3 plus R4. However, when backup card 122 is powered off (i.e., VDD on control circuit 106 and VCM buffer circuit 104 is 0 V), the control voltage CTL on the gate of transistor NM1 provided by control circuit 106 has a zero potential. The transient AC signals at terminals RTIP and RRING of the backup card may provide a negative voltage to terminals RTIP and/or RRING. The negative voltage at terminal RTIP or RRING may be clamped by ESD transistors (not shown) coupled to terminals RTIP and RRING to −VD, where VD is the threshold voltage of the ESD transistor. The negative potential is applied to the drain and/or source terminal of transistor NM1 through resistors R1 and/or R2. Because the gate potential is 0 V, transistor NM1 may be turned on by the voltage across the gate and the drain or source terminal. Thus, a low impedance circuit may exist in backup card 122 when the power is off.
In the pin-pin connection mode as shown in FIG. 2, primary card 120 and backup card 122 are coupled to transmission lines through one transformer 128. Terminals RTIP and RRING of backup card 122 are coupled to terminals RTIP and RRING of the primary card 120. Primary card 120 may include a VCM buffer circuit as shown in the circuit in FIG. 3. When primary card 120 is operating, the VCM buffer circuit of primary card 120 provides a DC bias to primary card 120. The DC bias also applies to backup card 122 through terminals RTIP and RRING of backup card 122. When backup card 122 is powered off, a DC current path may be formed through resistors R3 and R4. Another DC current path may also be formed through the monitor switches 132 and 134 and internal circuit coupled to monitor switches 132 and 134. A DC current path may also be formed through a neighboring channel (not shown) which can be coupled to backup card 122 through a monitor switch 136. Those DC current paths may affect the potential on RTIP and RRING of backup card 122, and may make the potential on RTIP and RRING far below Vref. Upon receipt of a full range of AC signals from the transmission lines, potentials at terminals RTIP and RRING may become negative, which may be clamped by the ESD protection circuit to −VD. Transistor NM1 is then turned on and a low impedance differential signal path appears between RTIP and RRING. The low impedance path may affect the function of primary card 120.
Therefore, there is a need for a simple and efficient input termination circuit that presents high impedance at power off and that is applicable for both line connection mode and pin-pin connection mode.